Modern electronic equipments often require circuits for biasing pairs of complementary output transistors. For instance, solid state, high power, audio frequency and operation amplifiers usually include pairs of complementary output power transistors for driving electrical loads and bias circuits, which generally are coupled between a supply of power and these complementary output transistors. Such bias circuits are required to provide quiescent or bias voltages and currents of known magnitudes to the complementary transistors for operating them Class AB to facilitate lowered power supply current drain as compared to Class A during quiescent operation and lowered crossover distortion as compared to Class B during dynamic operation. In some instances, it is desirable for such bias circuits to be manufactured in monolithic integrated circuit form to facilitate low cost, minimal space requirements and maximum reliability. In addition, it is often desirable for the Class AB bias circuits to provide compensation for the temperature induced voltage and current changes and process induced parameter variations in the complementary output transistors, which may be of either a monolithic or a discrete nature.
Prior art bias circuits have utilized NPN type monolithic devices for biasing and providing temperature and process compensation to the complementary NPN and PNP output transistors. Such NPN bias devices can successfully temperature compensate the complementary output NPN transistors even though the saturation current (I.sub.es) of such output transistors typically can vary over a ten-to-one ratio because of process variations. Moreover, the changes in the NPN type biasing device compensates for similar changes in the structure and composition of the NPN complementary output transistor from wafer to wafer. Unfortunately, such changes in structure and composition of NPN bias devices do not compensate for process and temperature induced changes in the characteristics of PNP complementary output transistors.
Other prior art bias circuits utilize series connected NPN and PNP devices in an attempt to overcome the foregoing problem. In general, the base-to-emitter voltage of a junction varies inversely with the size of the junction and directly with the magnitude of the current through the junction. Thus, the larger the junction the smaller the base-to-emitter voltage produced for a given amount of current through the junction. Thus, monolithic devices having small junctions can produce a desired bias voltage in response to a small current for biasing the larger junction of a complementary output transistor operating at a quiescent current level of a greater magnitude than the current through the bias device. Since monolithic PNP complementary transistors are larger than NPN complementary transistors, the series connected PNP bias device must have a larger geometry than if the PNP biasing device didn't have to conduct the same current as the NPN bias device. Thus, bias networks including series connected NPN and PNP bias devices having the same current are undesirable because of the unnecessarily large amount of die area required for the PNP bias device. Thus, bias circuits including only NPN bias devices or series driven NPN and PNP bias devices are unsatisfactory for some applications. Moreover, such prior art circuits sometimes draw undesirably large currents and are difficult to design for providing precise and predictable current control.